HCS12 datasheet(80/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

are used. If the CPU attempts to execute one of the unimplemented

opcodes on page 2, an opcode trap interrupt occurs. Traps are essentially

interrupts that share the $FFF8:$FFF9 interrupt vector.

The RTI instruction is used to terminate all exception handlers, including

interrupt service routines. RTI first restores the CCR, B:A, X, Y, and the

return address from the stack. If no other interrupt is pending, normal

execution resumes with the instruction following the last instruction that

executed prior to interrupt.

Table 5-22 is a summary of interrupt instructions.

Table 5-22. Interrupt Instructions

Mnemonic

Function

Operation

RTI

Return

from interrupt

(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP

(M(SP) : M(SP+1)) ⇒ B : A; (SP) + $0002 ⇒ SP

(M(SP) : M(SP+1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP

(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) + $0002 ⇒ SP

(M(SP) : M(SP+1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP

SWI

Software interrupt

SP – 2

⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; B : A ⇒ M(SP) : M(SP+1)

SP – 1

⇒ SP; CCR ⇒ M(SP)

TRAP

Unimplemented

opcode interrupt

SP – 2

⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)

SP – 2

⇒ SP; B : A ⇒ M(SP) : M(SP+1)

SP – 1

⇒ SP; CCR ⇒ M(SP)

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