HCS12 datasheet(42/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

Move instructions do not support indirect modes, 9-bit, or 16-bit offset

modes requiring extra extension bytes. There are special considerations

when using PC-relative addressing with move instructions. The original

M68HC12 implemented the instruction queue slightly differently than the

newer HCS12. In the older M68HC12 implementation, the CPU did not

maintain a pointer to the start of the instruction after the current instruction

(what the user thinks of as the PC value during execution). This caused an

offset for PC-relative move instructions.

PC-relative addressing uses the address of the location immediately

following the last byte of object code for the current instruction as a

reference point. The CPU12 normally corrects for queue offset and for

instruction alignment so that queue operation is transparent to the user.

However, in the original M68HC12, move instructions pose three special

problems:

• Some moves use an indexed source and an indexed destination.

• Some moves have object code that is too long to fit in the queue all at

one time, so the PC value changes during execution.

• All moves do not have the indexed postbyte as the last byte of object

code.

These cases are not handled by automatic queue pointer maintenance, but

it is still possible to use PC-relative indexing with move instructions by

providing for PC offsets in source code.

Table 3-3 shows PC offsets from the location immediately following the

current instruction by addressing mode.

Table 3-3. PC Offsets for MOVE Instructions (M68HC12 Only)

MOVE Instruction

Addressing Modes

Offset Value

MOVB

IMM

⇒ IDX

EXT

⇒ IDX

IDX

⇒ EXT

–2

IDX

⇒ IDX

–1 for first operand

+1 for second operand

MOVW

IMM

⇒ IDX

EXT

⇒ IDX

IDX

⇒ EXT

–2

IDX

⇒ IDX

–1 for first operand

+1 for second operand

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