HCS12 datasheet(24/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

The status bits reflect the results of CPU operation as it executes

instructions. The five flags are:

• Half carry (H)

• Negative (N)

• Zero (Z)

• Overflow (V)

• Carry/borrow (C)

The half-carry flag is used only for BCD arithmetic operations. The N, Z, V,

and C status bits allow for branching based on the results of a previous

operation.

In some architectures, only a few instructions affect condition codes, so that

multiple instructions must be executed in order to load and test a variable.

Since most CPU12 instructions automatically update condition codes, it is

rarely necessary to execute an extra instruction for this purpose. The

challenge in using the CPU12 lies in finding instructions that do not alter the

condition codes. The most important of these instructions are pushes, pulls,

transfers, and exchanges.

It is always a good idea to refer to an instruction set summary (see

Appendix A. Instruction Reference) to check which condition codes are

affected by a particular instruction.

The following paragraphs describe normal uses of the condition codes.

There are other, more specialized uses. For instance, the C status bit is

used to enable weighted fuzzy logic rule evaluation. Specialized usages are

described in the relevant portions of this manual and in Section 6.

Instruction Glossary.

2.2.5.1 S Control Bit

Clearing the S bit enables the STOP instruction. Execution of a STOP

instruction normally causes the on-chip oscillator to stop. This may be

undesirable in some applications. If the CPU encounters a STOP instruction

while the S bit is set, it is treated like a no-operation (NOP) instruction and

continues to the next instruction. Reset sets the S bit.

HCS12 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc