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HCS12 Datasheet(PDF) 245 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 245 Page - Freescale Semiconductor, Inc |
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245 / 452 page  Glossary S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 245 Operation: (CCR) + (M) ⇒ CCR Description: Performs bitwise logical inclusive OR between the content of memory location M and the content of the CCR and places the result in the CCR. Each bit of the CCR after the operation is the logical OR of the corresponding bits of M and of CCR before the operation. To set one or more bits, set the corresponding bit of the mask equal to 1. Bits corresponding to 0s in the mask are not changed by the ORCC operation. Condition code bits are set if the corresponding bit was 1 before the operation or if the corresponding bit in the instruction-provided mask is 1. The X interrupt mask cannot be set by any software instruction. ORCC Logical OR CCR with Mask ORCC CCR Details: S X HIN Z V C ⇑ – ⇑⇑⇑⇑⇑⇑ Source Form Address Mode Object Code Access Detail HCS12 M68HC12 ORCC #opr8i IMM 14 ii P P |
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