HCS12 datasheet(270/452 Pages) FREESCALE

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Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

270

Freescale Semiconductor

Operation:

(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP

(M(SP) : M(SP+1)) ⇒ B : A; (SP) + $0002 ⇒ SP

(M(SP) : M(SP+1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP

(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) – $0002 ⇒ SP

(M(SP) : M(SP+1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP

Description:

Restores system context after interrupt service processing is completed.

The condition codes, accumulators B and A, index register X, the PC, and

index register Y are restored to a state pulled from the stack. The X mask

bit may be cleared as a result of an RTI instruction, but cannot be set if it

was cleared prior to execution of the RTI instruction.

If another interrupt is pending when RTI has finished restoring registers from

the stack, the SP is adjusted to preserve stack content, and the new vector

is fetched. This operation is functionally identical to the same operation in

the M68HC11, where registers actually are re-stacked, but is faster.

Condition codes take on the value pulled from the stack, except that the X

mask bit cannot change from 0 to 1. Software can leave the X bit set, leave

it cleared, or change it from 1 to 0, but it can be set only by a reset or by

recognition of an XIRQ interrupt.

RTI

Return from Interrupt

RTI

CCR Details:

HIN

∆⇓∆∆∆∆∆∆

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

RTI

(with interrupt pending)

INH

uUUUUPPP

uUUUUfVfPPP

uUUUUPPP

uUUUUVfPPP

HCS12 Datasheet(PDF) 270 Page - Freescale Semiconductor, Inc

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