HCS12 datasheet(386/452 Pages) FREESCALE

386 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

386

Freescale Semiconductor

ETBL oprx0_xysp

(M:M+1)+ [(B)

×((M+2:M+3) – (M:M+1))] ⇒ D

16-Bit Table Lookup and Interpolate

Initialize B, and index before ETBL.

<ea> points at first table entry (M:M+1)

and B is fractional part of lookup value

(no indirect addr. modes or extensions allowed)

IDX

18 3F xb

ORRffffffP

– – – –

∆ ∆ – ∆

C Bit is undefined

in HC12

EXG abcdxys,abcdxys

(r1)

⇔ (r2) (if r1 and r2 same size) or

$00:(r1)

⇒ r2 (if r1=8-bit; r2=16-bit) or

(r1low) ⇔ (r2) (if r1=16-bit; r2=8-bit)

r1 and r2 may be

A, B, CCR, D, X, Y, or SP

INH

B7 eb

– – – –

FDIV

(D)

÷ (X) ⇒ X; Remainder ⇒ D

16 by 16 Bit Fractional Divide

INH

18 11

OffffffffffO

– – – –

–

∆ ∆ ∆

IBEQ abdxys, rel9

(cntr) + 1

⇒ cntr

If (cntr) = 0, then Branch

else Continue to next instruction

Increment Counter and Branch if = 0

(cntr = A, B, D, X, Y, or SP)

REL

(9-bit)

04 lb rr

PPP (branch)

PPO (no

branch)

PPP

– – – –

IBNE abdxys, rel9

(cntr) + 1

⇒ cntr

if (cntr) not = 0, then Branch;

else Continue to next instruction

Increment Counter and Branch if

≠ 0

(cntr = A, B, D, X, Y, or SP)

REL

(9-bit)

04 lb rr

PPP (branch)

PPO (no

branch)

PPP

– – – –

IDIV

(D)

÷ (X) ⇒ X; Remainder ⇒ D

16 by 16 Bit Integer Divide (unsigned)

INH

18 10

OffffffffffO

– – – –

–

∆ 0 ∆

IDIVS

(D)

÷ (X) ⇒ X; Remainder ⇒ D

16 by 16 Bit Integer Divide (signed)

INH

18 15

OffffffffffO

– – – –

∆ ∆ ∆ ∆

INC opr16a

INC oprx0_xysp

INC oprx9,xysp

INC oprx16,xysp

INC [D,xysp]

INC [oprx16,xysp]

INCA

INCB

(M) + $01

⇒ M

Increment Memory Byte

(A) + $01

⇒ A

Increment Acc. A

(B) + $01

⇒ B

Increment Acc. B

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

72 hh ll

62 xb

62 xb ff

62 xb ee ff

62 xb

62 xb ee ff

rPwO

rPw

rPwO

frPwP

fIfrPw

fIPrPw

rOPw

rPw

rPOw

frPPw

fIfrPw

fIPrPw

– – – –

∆ ∆ ∆ –

INS

(SP) + $0001

⇒ SP

Translates to LEAS 1,SP

IDX

1B 81

– – – –

INX

(X) + $0001

⇒ X

Increment Index Register X

INH

– – – –

–

∆ – –

INY

(Y) + $0001

⇒ Y

Increment Index Register Y

INH

– – – –

–

∆ – –

JMP opr16a

JMP oprx0_xysp

JMP oprx9,xysp

JMP oprx16,xysp

JMP [D,xysp]

JMP [oprx16,xysp]

Routine address

⇒ PC

Jump

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

06 hh ll

05 xb

05 xb ff

05 xb ee ff

05 xb

05 xb ee ff

PPP

fPPP

fIfPPP

PPP

fPPP

fIfPPP

– – – –

Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

JSR opr8a

JSR opr16a

JSR oprx0_xysp

JSR oprx9,xysp

JSR oprx16,xysp

JSR [D,xysp]

JSR [oprx16,xysp]

(SP) – 2

⇒ SP;

RTNH:RTNL ⇒ M(SP):M(SP+1);

Subroutine address

⇒ PC

Jump to Subroutine

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

17 dd

16 hh ll

15 xb

15 xb ff

15 xb ee ff

15 xb

15 xb ee ff

SPPP

PPPS

fPPPS

fIfPPPS

PPPS

fPPPS

fIfPPPS

– – – –

LBCC rel16

Long Branch if Carry Clear (if C = 0)

REL

18 24 qq rr

OPPP/OPO

– – – –

LBCS rel16

Long Branch if Carry Set (if C = 1)

REL

18 25 qq rr

OPPP/OPO

– – – –

LBEQ rel16

Long Branch if Equal (if Z = 1)

REL

18 27 qq rr

OPPP/OPO

– – – –

LBGE rel16

Long Branch Greater Than or Equal

(if N

⊕ V = 0) (signed)

REL

18 2C qq rr

OPPP/OPO

– – – –

Table A-1. Instruction Set Summary (Sheet 6 of 14)

Source Form

Operation

Addr.

Mode

Machine

Coding (hex)

Access Detail

S X H I

N Z V C

HCS12

M68HC12

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