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HCS12 Datasheet(PDF) 147 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 147 Page - Freescale Semiconductor, Inc |
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147 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 147 Operation: 0 ⇒ I bit Description: Clears the I mask bit. This instruction is assembled as ANDCC #$EF. The ANDCC instruction can be used to clear any combination of bits in the CCR in one operation. When the I bit is cleared, interrupts are enabled. There is a 1-cycle (bus clock) delay in the clearing mechanism for the I bit so that, if interrupts were previously disabled, the next instruction after a CLI will always be executed, even if there was an interrupt pending prior to execution of the CLI instruction. CLI Clear Interrupt Mask CLI CCR Details: S X HIN Z V C ––– 0 –––– I: 0; cleared Source Form Address Mode Object Code Access Detail HCS12 M68HC12 CLI translates to... ANDCC #$EF IMM 10 EF P P |
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