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HCS12 Datasheet(PDF) 200 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 200 Page - Freescale Semiconductor, Inc |
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200 / 452 page  Instruction Glossary S12CPUV2 Reference Manual, Rev. 4.0 200 Freescale Semiconductor Operation: If Z + (N ⊕ V) = 0, then (PC) + $0004 + Rel ⇒ PC For signed two’s complement numbers, If (Accumulator) > (Memory), then branch Description: LBGT can be used to branch after subtracting or comparing signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is greater than or equal to the value in A. See 3.8 Relative Addressing Mode for details of branch execution. LBGT Long Branch if Greater Than Zero LBGT CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 LBGT rel16 REL 18 2E qq rr OPPP/OPO (1) 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken. OPPP/OPO(1) Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r>m LBGT 18 2E Z + (N ⊕ V) = 0 r ≤m LBLE 18 2F Signed r ≥m LBGE 18 2C N ⊕ V = 0 r<m LBLT 18 2D Signed r=m LBEQ 18 27 Z = 1 r ≠m LBNE 18 26 Signed r ≤m LBLE 18 2F Z + (N ⊕ V) = 1 r>m LBGT 18 2E Signed r<m LBLT 18 2D N ⊕ V = 1 r ≥m LBGE 18 2C Signed r>m LBHI 18 22 C + Z = 0 r ≤m LBLS 18 23 Unsigned r ≥m LBHS/LBCC 18 24 C = 0 r<m LBLO/LBCS 18 25 Unsigned r=m LBEQ 18 27 Z = 1 r ≠m LBNE 18 26 Unsigned r ≤m LBLS 18 23 C + Z = 1 r>m LBHI 18 22 Unsigned r<m LBLO/LBCS 18 25 C = 1 r ≥m LBHS/LBCC 18 24 Unsigned Carry LBCS 18 25 C = 1 No Carry LBCC 18 24 Simple Negative LBMI 18 2B N = 1 Plus LBPL 18 2A Simple Overflow LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple r=0 LBEQ 18 27 Z = 1 r ≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional |
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