UJA1076 datasheet(6/47 Pages) NXP

6 / 47 page

UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

6 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

The exposed die pad at the bottom of the package allows for better heat dissipation from

the SBC via the printed circuit board. The exposed die pad is not connected to any active

part of the IC and can be left floating, or can be connected to GND.

Functional description

The UJA1076 combines the functionality of a high-speed CAN transceiver, two voltage

regulators and a watchdog (UJA1076/xx/WD versions) in a single, dedicated chip. It

handles the power-up and power-down functionality of the ECU and ensures advanced

system reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the

activation of external switches. Additionally, it provides a periodic control signal for pulsed

testing of wake-up switches, allowing low-current operation even when the wake-up

switches are closed in Standby mode.

All transceivers are optimized to be highly flexible with regard to bus topologies. In

particular, the high-speed CAN transceiver is optimized to reduce ringing (bus reflections).

V1, the main voltage regulator, is designed to power the ECU's microcontroller, its

peripherals and additional external transceivers. An external PNP transistor can be added

to improve heat distribution. V2 supplies the integrated high-speed CAN transceiver. The

watchdog is clocked directly by the on-chip oscillator and can be operated in Window,

Timeout and Off modes.

WAKE1

local wake-up input 1

WAKE2

local wake-up input 2

5 V voltage regulator output for CAN

CANH

CANH bus line

CANL

CANL bus line

GND

ground

SPLIT

CAN bus common mode stabilization output

i.c.

internally connected; should be left floating

i.c.

internally connected; should be left floating

i.c.

internally connected; should be left floating

WBIAS

control pin for external wake biasing transistor

VEXCC

current measurement for external PNP transistor; this pin is connected to

the collector of the external PNP transistor

TEST2

test pin; pin should be connected to ground

VEXCTRL

control pin of the external PNP transistor; this pin is connected to the base

of the external PNP transistor

BAT

battery supply for the SBC

Table 2.

Pin description …continued

Symbol

Description

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