UJA1076 datasheet(11/47 Pages) NXP

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UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

11 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2.3 WD_and_Status register

[1]

Bit NWP is set to it’s default value (100) after a reset.

Table 4.

WD_and_Status register

Bit

Symbol

Access Power-on

default

Description

15:13 A2, A1, A0

000

R/W

access status

0: register set to read/write

1: register set to read only

WMC

R/W

watchdog mode control

0: Normal mode: watchdog in Window mode; Standby mode: watchdog in

Timeout mode

1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in

Off mode

10:8

NWP[1]

R/W

100

nominal watchdog period

000: 8 ms

001: 16 ms

010: 32 ms

011: 64 ms

100: 128 ms

101: 256 ms

110: 1024 ms

111: 4096 ms

WOS/SWR

R/W

watchdog off status/software reset

0: WDOFF pin LOW; watchdog mode determined by bit WMC

1: watchdog disabled due to HIGH level on pin WDOFF; results in software

reset

V1S

V1 status

0: V1 output voltage above 90 % undervoltage recovery threshold

(Vuvr;see Table 10)

1: V1 output voltage below 90 % undervoltage detection threshold

(Vuvd;see Table 10)

V2S

V2 status

0: V2 output voltage above undervoltage release threshold

(Vuvr;see Table 10)

1: V2 output voltage below undervoltage detection threshold

(Vuvd;see Table 10)

WLS1

wake-up 1 status

0: WAKE1 input voltage below switching threshold (Vth(sw))

1: WAKE1 input voltage above switching threshold (Vth(sw))

WLS2

wake-up 2 status

0: WAKE2 input voltage below switching threshold (Vth(sw))

1: WAKE2 input voltage above switching threshold (Vth(sw))

2:0

reserved

000

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