UJA1076 datasheet(13/47 Pages) NXP

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UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

13 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2.5 Int_Control register

Table 6.

Int_Control register

Bit

Symbol

Access

Power-on

default

Description

15:13

A2, A1, A0 R

010

R/W

access status

0: register set to read/write

1: register set to read only

V1UIE

R/W

V1 undervoltage interrupt enable

0: V1 undervoltage warning interrupts cannot be requested

1: V1 undervoltage warning interrupts can be requested

V2UIE

R/W

V2 undervoltage interrupt enable

0: V2 undervoltage warning interrupts cannot be requested

1: V2 undervoltage warning interrupts can be requested

9:8

reserved

7:6

WIC1

R/W

wake-up interrupt 1 control

00: wake-up interrupt 1 disabled

01: wake-up interrupt 1 on rising edge

10: wake-up interrupt 1 on falling edge

11: wake-up interrupt 1 on both edges

5:4

WIC2

R/W

wake-up interrupt 2 control

00: wake-up interrupt 2 disabled

01: wake-up interrupt 2 on rising edge

10: wake-up interrupt 2 on falling edge

11: wake-up interrupt 2 on both edges

STBCC

R/W

CAN standby control

0: When the SBC is in Normal mode (MC = 1x):

CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared

regardless of V2 output voltage.

When the SBC is in Standby/Sleep mode (MC = 0x):

CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up

interrupts cannot be requested.

1: CAN is in Lowpower mode with bus wake-up detection enabled,

regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be

requested.

RTHC

R/W

reset threshold control

0: The reset threshold is set to the 90 % V1 undervoltage detection voltage

(Vuvd; see Table 10)

1: The reset threshold is set to the 70 % V1 undervoltage detection voltage

(Vuvd; see Table 10)

WSE1

R/W

WAKE1 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

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