UJA1076 datasheet(10/47 Pages) NXP

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UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

10 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2 SPI

6.2.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing registers to be read back by the

application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCSN: SPI chip select; active LOW

• SCK: SPI clock; default level is LOW due to low-power concept

• SDI: SPI data input

• SDO: SPI data output; floating when pin SCSN is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge (see Figure 4).

6.2.2 Register map

The first three bits (A2, A1 and A0) of the message header define the register address.

The fourth bit (RO) defines the selected register as read/write or read only.

Fig 4.

SPI timing protocol

SCS

SCK

sampled

floating

mce634

MSB

LSB

MSB

LSB

SDI

SDO

Table 3.

Address bits 15, 14 and 13

Write access bit 12 = 0

Read/Write access bits 11... 0

000

0 = read/write, 1 = read only

WD_and_Status register

001

0 = read/write, 1 = read only

Mode_Control register

010

0 = read/write, 1 = read only

Int_Control register

011

0 = read/write, 1 = read only

Int_Status register

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