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UJA1076 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # UJA1076
Description  High-speed CAN core system basis chip
PDF  47 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

UJA1076 Datasheet(HTML) 8 Page - NXP Semiconductors

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UJA1076_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 May 2010
8 of 47
NXP Semiconductors
UJA1076
High-speed CAN core system basis chip
Fig 3.
UJA1076 system controller
V1: ON
V2: OFF
CAN: Lowpower/Off
watchdog: Timeout/Off
MC = 00
Standby
watchdog
trigger
V1: ON
V2: ON/OFF
CAN: Active/Lowpower
watchdog: Window/
Timeout/Off
MC = 1x
Normal
V1: OFF
V2: OFF
CAN: Lowpower/Off
watchdog: OFF
RSTN: LOW
MC = 01
Sleep
successful
watchdog
trigger
watchdog overflow or
V1 undervoltage
V1: OFF
V2: OFF
CAN: Off and
high resistance
watchdog: OFF
INTN: HIGH
Off
VBAT below
power-on threshold Vth(det)pon
VBAT below
power-off threshold Vth(det)poff
(from all modes)
V1: OFF
V2: OFF
limp home = LOW (active)
CAN: Off and
high resistance
watchdog: OFF
Overtemp
from Standby or Normal
chip temperature above
OTP activatrion threshold Tth(act)otp
chip temperature below
OTP release threshold Tth(rel)otp
VBAT above
power-on threshold Vth(det)pon
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
wake-up event if enabled
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
reset event or
MC = 00
MC = 10 or MC = 11
015aaa110



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