EPC4 datasheet(17/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–17

Functional Description

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Dynamic Configuration (Page Mode)

The dynamic configuration (or page mode) feature allows the enhanced configuration

device to store up to eight different sets of designs for all the FPGAs in your system.

You can then choose which page (set of configuration files) the enhanced

configuration device should use for FPGA configuration.

Dynamic configuration or the page mode feature enables you to store a minimum of

two pages: a factory default or fail-safe configuration, and an application

configuration. The fail-safe configuration page could be programmed during system

production, while the application configuration page could support remote or local

updates. These remote updates could add or enhance system features and

performance. However, with remote update capabilities comes the risk of possible

corruption of configuration data. In the event of such a corruption, the system could

automatically switch to the fail-safe configuration and avoid system downtime.

The enhanced configuration device page mode feature works with the Stratix Remote

System Configuration feature, to enable intelligent remote updates to your systems.

f For more information about remotely updating Stratix FPGAs, refer to Remote System

Configuration with Stratix & Stratix GX Devices in the Stratix Device Handbook.

The three PGM[2..0] input pins control which page is used for configuration, and

these pins are sampled at the start of each configuration cycle when OE goes high. The

page mode selection allows you to dynamically reconfigure the functionality of your

FPGA by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as

the default page and the PGM[2] pin is the most significant bit (MSB).

1 The PGM[2..0] input pins must not be left floating on your board, regardless of

whether this feature is used or not. When this feature is not used, connect the

PGM[2..0]

pins to GND to select the default page 000.

The enhanced configuration device pages are dynamically sized regions in memory.

The start address and length of each page is programmed into the option-bit space of

the flash memory during initial programming. All subsequent configuration cycles

will sample the PGM[] pins and use the option-bit information to jump to the start of

the corresponding configuration page. Each page must have configuration files for all

FPGAs in your system that are connected to that enhanced configuration device.

For example, if your system requires three configuration pages and includes two

FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the

configuration device.

Furthermore, all enhanced configuration device configuration schemes (PS, FPP, and

concurrent PS) are supported with the page-mode feature. The number of pages,

devices, or both, that can be configured using a single enhanced configuration device

is only limited by the size of the flash memory.

f For detailed information about the page-mode feature implementation and

programming file generation steps using the Quartus II software, refer to the Altera

Enhanced Configuration Devices chapter in volume 2 of the Configuration Handbook.

EPC4 Datasheet(PDF) 17 Page - Altera Corporation

EPC4 Datasheet(HTML) 17 Page - Altera Corporation

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