1–24

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Pin Description

Configuration Handbook (Complete Two-Volume Set)

© December 2009

Altera Corporation

BYTE#

Input

Flash byte-enable pin and is only available for enhanced configuration devices in

the 100-pin PQFP package.

external flash interface (the controller uses the flash in 16-bit mode). For Intel

pull-up resistor.

Notes to Table 1–9:

(1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections

from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the

two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE# pin from controller to F-WE# pin from the

flash memory).

(2) For more information, refer to the Process Change Notification PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16

Enhanced Configuration Devices and Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16 white paper.

Table 1–10. JTAG Interface Pins and Other Required Controller Pins

Pin Name

Pin Type

Description

TDI

Input

JTAG data input pin.

TDO

Output

JTAG data output pin.

Do not connect this pin if the JTAG circuitry is not used (leave floating).

TCK

Input

JTAG clock pin.

Connect this pin to GND if the JTAG circuitry is not used.

TMS

Input

JTAG mode select pin.

PGM[2..0]

Input

These three input pins select one of the eight pages of configuration data to

configure the FPGAs in the system.

Connect these pins on the board to select the page specified in the Quartus II

software when generating the enhanced configuration device POF. PGM[2] is the

MSB. The default selection is page 0; PGM[2..0]=000. These pins must not be

left floating.

EXCLK

Input

Optional external clock input pin that can be used to generate the configuration

clock (DCLK).

When an external clock source is not used, connect this pin to a valid logic level

(high or low) to prevent a floating-input buffer. If EXCLK is used, toggling the

EXCLK

input pin after the FPGA enters user mode will not effect the enhanced

configuration device operation.

PORSEL

Input

This pin selects a 2-ms or 100-ms POR counter delay during power up. When

PORSEL

is low, POR time is 100 ms. When PORSEL is high, POR time is 2 ms.

This pin must be connected to a valid logic level.

TM0

Input

For normal operation, this test pin must be connected to GND.

TM1

Input

Table 1–9. External Flash Interface Pins (Part 3 of 3)

Pin Name

Pin Type

Description