EPC4 datasheet(25/34 Pages) ALTERA

25 / 34 page

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–25

Power-On Reset

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Power-On Reset

The POR circuit keeps the system in reset until power-supply voltage levels have

stabilized. The POR time consists of the VCC ramp time and a user-programmable

POR delay counter. When the supply is stable and the POR counter expires, the POR

circuit releases the OE pin. The POR time can be further extended by an external

device by driving the OE pin low.

1 Do not execute JTAG or ISP instructions until POR is complete.

The enhanced configuration device supports a programmable POR delay setting. You

can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms

for systems that require fast power-up. The PORSEL input pin controls this POR

delay; a logic-high level selects the 2-ms delay, while a logic-low level selects the

100-ms delay.

The enhanced configuration device can enter reset under the following conditions:

■

The POR reset starts at initial power-up during VCC ramp-up or if VCC drops

below the minimum operating condition anytime after VCC has stabilized

■

The FPGA initiates reconfiguration by driving nSTATUS low, which occurs if the

FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted

■

The controller detects a configuration error and asserts OE to begin

re-configuration of the Altera FPGA (for example, when CONF_DONE stays low

after all configuration data has been transmitted)

Power Sequencing

Altera requires that you power-up the FPGA's VCCINT supply before the enhanced

configuration device's POR expires.

Power up needs to be controlled so that the enhanced configuration device’s OE signal

goes high after the CONF_DONE signal is pulled low. If the EEPC device exits POR

before the FPGA is powered up, the CONF_DONE signal will be high because the

pull-up resistor is holding this signal high. When the enhanced configuration device

exits POR, OE is released and pulled high by a pull-up resistor. Since the enhanced

configuration device samples the nCS signal on the rising edge of OE, it detects a high

level on CONF_DONE and enters an idle mode. DATA and DCLK outputs will not toggle

in this state and configuration will not begin. The enhanced configuration device will

only exit this mode if it is powered down and then powered up correctly.

1 To ensure the enhanced configuration device enters configuration mode properly, you

must ensure that the FPGA completes power-up before the enhanced configuration

device exits POR.

The pin-selectable POR time feature is useful for ensuring this power-up sequence.

The enhanced configuration device has two POR settings, 2 ms when PORSEL is set to

a high level and 100 ms when PORSEL is set to a low level. For more margin, the

100-ms setting can be selected to allow the FPGA to power-up before configuration is

attempted.

EPC4 Datasheet(PDF) 25 Page - Altera Corporation

EPC4 Datasheet(HTML) 25 Page - Altera Corporation

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