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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

IEEE Std. 1149.1 (JTAG) Boundary-Scan

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

IEEE Std. 1149.1 (JTAG) Boundary-Scan

The enhanced configuration device provides JTAG BST circuitry that complies with

the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed

before or after configuration, but not during configuration.

Figure 1–6 shows the timing requirements for the JTAG signals.

Table 1–13 lists the timing parameters and values for the enhanced configuration

device.

Figure 1–6. JTAG Timing Waveforms

TDO

TCK

tJPZX

tJPCO

tJPH

tJPXZ

tJCP

tJPSU

tJCL

tJCH

TDI

TMS

Signal

to be

Captured

Signal

to be

Driven

tJSZX

tJSSU

tJSH

tJSCO

tJSXZ

Table 1–13. JTAG Timing Parameters and Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

—

tJCH

TCK

clock high time

—

tJCL

TCK

clock low time

—

tJPSU

JTAG port setup time

—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock output

—

tJPZX

JTAG port high impedance to valid output

—

tJPXZ

JTAG port valid output to high impedance

—

tJSSU

Capture register setup time

—

tJSH

Capture register hold time

—

tJSCO

Update register clock to output

—

tJSZX

Update register high-impedance to valid output

—

tJSXZ

Update register valid output to high impedance

—

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