Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–27

Programming and Configuration File Support

© December 2009

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

the BSDL files provided at the Altera website.

Enhanced configuration devices can also be programmed by third-party flash

programmers or on-board processors using the external flash interface. Programming

files (.pof) can be converted to an Intel HEX format file (.hexout) using the Quartus II

Convert Programming Files

utility, for use with the programmers or processors.

You can also program the enhanced configuration devices using the Quartus II

software, the Altera Programming Unit (APU), and the appropriate configuration

device programming adapter. Table 1–12 lists which programming adapter to use

with each enhanced configuration device.

INIT_CONF

00 0110 0001

This function initiates the FPGA re-configuration process by pulsing the

nINIT_CONF

pin low, which is connected to the FPGA nCONFIG pin. After

this instruction is updated, the nINIT_CONF pin is pulsed low when the JTAG

state machine enters Run-Test/Idle state. The nINIT_CONF pin is then

released and nCONFIG is pulled high by the resistor after the JTAG state

machine goes out of Run-Test/Idle state. The FPGA configuration starts after

nCONFIG

goes high. As a result, the FPGA is configured with the new

configuration data stored in flash via ISP. This function can be added to your

programming file (

.pof, .jam, .jbc) in the Quartus II software by enabling the

Initiate configuration after programming option in the Programmer options

window (Options menu).

PENDCFG

00 0110 0101

This optional function can be used to hold the nINIT_CONF pin low during

JTAG-based ISP of the enhanced configuration device. This feature is useful

when the external flash interface is controlled by an external FPGA/processor.

This function prevents contention on the flash pins when both the controller and

external device try to access the flash simultaneously. Before the enhanced

configuration device’s controller can access the flash memory, the external

FPGA/processor needs to tri-state its interface to flash.This can be ensured by

resetting the FPGA using the nINIT_CONF, which drives the nCONFIG pin and

keeps the external FPGA/processor in the “reset” state. The nINIT_CONF pin is

released when the initiate configuration (INIT_CONF) JTAG instruction is

issued.

Note to Table 1–11:

(1) Enhanced configuration device instruction register length is 10 and boundary scan length is 174.

JTAG Instruction

OPCODE

Description

Table 1–12. Programming Adapters

Device

Package

Adapter

EPC16

88-pin UFBGA

PLMUEPC-88

100-pin PQFP

PLMQEPC-100

EPC8

100-pin PQFP

PLMQEPC-100

EPC4

100-pin PQFP

PLMQEPC-100