EPC4 datasheet(20/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

The controller chip features a programmable oscillator that can output four different

frequencies. The various settings generate clock outputs at frequencies as high as 10,

33, 50, and 66 MHz, as listed in Table 1–7.

Clock source, oscillator frequency, and clock divider (N) settings can be made in the

Quartus II software, by accessing the Configuration Device Options inside the

Device Settings

window or the Convert Programming Files window. The same

window can be used to select between the internal oscillator and the external clock

(EXCLK) input pin as your configuration clock source. The default setting selects the

internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1.

f For more information about making the configuration clock source, frequency, and

divider settings, refer to the Altera Enhanced Configuration Devices chapter in volume 2

of the Configuration Handbook.

Flash In-System Programming (ISP)

The flash memory inside enhanced configuration devices can be programmed

in-system via the JTAG interface and the external flash interface. JTAG-based

programming is facilitated by the configuration controller in the enhanced

configuration device. External flash interface programming requires an external

processor or FPGA to control the flash.

1 The enhanced configuration device flash memory supports 100,000 erase cycles.

JTAG-based Programming

The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in enhanced configuration

devices to facilitate the testing of its interconnection and functionality. Enhanced

configuration devices also support the ISP mode. The enhanced configuration device

is compliant with the IEEE Std. 1532 draft 2.0 specification.

The JTAG unit of the configuration controller communicates directly with the flash

memory. The controller processes the ISP instructions and performs the necessary

flash operations. The enhanced configuration devices support a maximum JTAG TCK

frequency of 10 MHz.

During JTAG-based ISP, the external flash interface is not available. Before the JTAG

interface programs the flash memory, an optional JTAG instruction (PENDCFG) can be

used to assert the FPGA’s nCONFIG pin (via the nINIT_CONF pin). This will keep the

FPGA in reset and terminate any internal flash access. This function prevents

contention on the flash pins when both JTAG ISP and an external FPGA or processor

try to access the flash simultaneously. The nINIT_CONF pin is released when the

initiate configuration (nINIT_CONF) JTAG instruction is updated. As a result, the

FPGA is configured with the new configuration data stored in flash.

Table 1–7. Internal Oscillator Frequencies

Frequency Setting

Min (MHz)

Typ (MHz)

Max (MHz)

6.4

8.0

10.0

21.0

26.5

33.0

32.0

40.0

50.0

42.0

53.0

66.0

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