SC493 datasheet(15/28 Pages) SEMTECH

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SC493

Ultrasonic Power-save

When ultrasonic PSAVE is enabled (PSV1,0 =10) the

minimum operating frequency in power save for the

SC493 is set by UPSV1,0 bits . This is accomplished by

using a built-in timer that detects the time between con-

secutive high-side gate pulses.

As soon as the time exceeds the the programmed upper

limit, the bottom gate is turned on. This prevents the con-

troller from going below the set limit in frequency when

the power save is enabled. Figure 2 shows ultrasonic

power-save operation.

FB Ripple

Voltage (VFB)

FB threshold

(500mV)

Inductor

Current

(0A)

40µsec time-out

Minimum FSW ~ 20kHz

After the 40µsec time-out, DL drives high if VFB

has not reached the FB threshold.

DH On-Time is triggered when

VFB reaches the FB Threshold

On-time

(TON)

Figure 2 — Ultrasonic Power-save (UPSV 1,0 = 11)

Power Good Output

The Power Good (PGD) output is an open-drain output

which requires a pull-up resistor. When the FB voltage falls

lower than 80% (typical) of the nominal voltage, PGD is

pulled low. It is held low until the FB voltage rises above

90% (typical) of the nominal voltage. PGD is held low

during start-up and will not be allowed to transition high

until soft-start is completed. PGD also transitions low if the

FB voltage rises above 120% (typical) of the nominal

voltage, it is held low until the FB voltage drops below 110%

(typical) of the nominal voltage.

UVLO and POR

Under-Voltage Lockout (UVLO) circuitry inhibits switching

and tri-states the output until VDD rises above 2.8V. An

internal Power-On Reset (POR) occurs until VDD exceeds

2.8V, which resets the internal registers, enables the I2C

interface, and resets the soft-start circuitry.

Smart Power-save Protection

Active loads may leak current from a higher voltage into

the switcher output. Under light load conditions with

power-save enabled, this can force V

OUT to slowly rise and

reach the over-voltage threshold. Smart power-save pre-

vents this condition. When the FB voltage exceeds 10%

above nominal (exceeds 550mV), the device immediately

disables power-save, and DL drives high to turn on the

low-side MOSFET. This draws current from V

OUT through

the inductor and causes V

OUT to fall. When VFB drops back

to the 500mV trip point, a normal T

ON switching cycle

begins. This method prevents an OVP fault and also cycles

energy from V

OUT back to VIN. The device will return to

power-save operation on the next switching cycle if the

load remains light. Smart Power-Save allows the user to

minimize operating power by allowing the use of power

save mode in load conditions that would normally require

the use of forced continuous conduction mode. Figure 3

shows typical waveforms for the Smart Power-save

feature.

threshold

High-side

Drive (DH)

Low-side

Drive (DL)

VOUT drifts up to due to leakage

current flowing into COUT

DH and DL off

DL turns on when Smart

PSAVE threshold is reached

Smart Power Save

Threshold (550mV)

DL turns off when FB

threshold is reached

Single DH on-time pulse

after DL turn-off

VOUT discharges via inductor

and low-side MOSFET

Normal DL pulse after DH

on-time pulse

Normal VOUT ripple

Figure 3 — Smart Power-save

Applications Information (continued)

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