SC493 datasheet(18/28 Pages) SEMTECH

18 / 28 page

SC493

Applications Information (continued)

Stability Considerations

Unstable operation occurs in two related but distinctly dif-

ferent ways — double-pulsing and fast-feedback loop insta-

bility. Double-pulsing occurs due to switching noise seen at

the FB input or because the FB ramp voltage is too low. This

causes the high side to turn on prematurely after the 250ns

minimum off-time has been completed. Double-pulsing

will result in higher ripple voltage at the output, but in most

applications will not adversely affect operation. However, In

some cases double-pulsing can indicate the presence of

loop instability, which is caused by insufficient ESR.

The best method for checking stability is to apply a zero-to-

full load transient and observe the output voltage ripple

envelope for overshoot and ringing. Over one cycle of

ringing after the initial step is an indication that the ESR

should be increased. One simple way to solve this problem

is to add trace resistance in the high current output path. A

side effect of adding trace resistance is output voltage

droop with load.

The on-time control regulates the valley of the output

ripple voltage. This ripple voltage consists of a term gener-

ated by the ESR of the output capacitor and a term based

upon the capacitance charging and discharging during

the switching cycle. A minimum ESR is required to gener-

ate the required ripple voltage for regulation. For stability

the ESR zero of the output capacitor should be lower than

approximately one-third of the switching frequency. The

formula for minimum ESR is shown by the next equation.

OUT

MIN

ESR

Where f

SW is the switching frequency.

For applications using ceramic output capacitors, the ESR

is normally too small to meet the above ESR criteria. In

these applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in the Figure 5.

COUT

Low-side

High-side

Figure 5 – Virtual ESR Network

This network creates a ramp voltage across C

L which is

analogous to the ramp voltage generated across the ESR

of a standard capacitor. This ramp is then capacitively

coupled into the FB pin via capacitor C

C. This circuit is ana-

lyzed as follows. The AC equivalent circuit used to calcu-

late the injected signal at FB pin is shown in Figure 6

(without considering the output ripple voltage).

FB pin

VSW

VINJ

VRIPPLE

Figure 6 – AC Equivalent Circuit

The DC voltage at V

RIPPLE is the same as VSW, which is the

same as V

OUT. The current through resistance RL during the

on time is shown by the next equation.

SC493 Datasheet(PDF) 18 Page - Semtech Corporation

SC493 Datasheet(HTML) 18 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL