SC493

22

Switching and Status Control — Register 1

Name

Bit

Description

Description

ENSW

01h[0]

Enable Switching

This bits controls whether the output is enabled or not.

0: The output is disabled, both high side and low side switches are off.

1: power-on delay and soft start process can start when this bit is 1 and the EN pin is pulled

high.

CLF

01h[1]

Clear Fault Status

Set to clear fault indicator flags (UVO, OVO, OT, ILIM, BO, & DNS). This bit is self clearing.

EnIntLd

01h{2}

Enable Internal Load

Set to enable internal pull down on VOUT when slewing down.

Timing Control — Registers 2 and 3

These registers provide software control over key timing parameters of the controller: frequency setting (Freq), Power-

On Delay (POD) time, Soft-Start Time (SST) setting, power save (PSV) mode control, and minimum switching frequency

in Ultrasonic Power Save (UPSV) mode. The details of each setting are listed in the table below.

Name

Bit

Definition

Description

Freq1

Freq0

02h

[1:0]

Frequency Setting

2 bits that control the switching frequency from 250kHz to 1MHz.

00 : 250kHz

01 : 500kHz

10 : 750kHz

11 : 1MHz

POD2

POD1

POD0

02h

[4:2]

Power-on Delay Time

3 bits that control the power-on delay from 0μs to 16ms.

000 : 0

001 : 250

010 : 500

011 : 1000

100 :

101 : 4

110 : 8

111 : 16ms

SST2

SST1

SST0

03h

[4:2]

Soft Start Time Setting

3 bits that control the soft start time from 250μs to 16ms.

000 : 250

001 : 500

010 : 1000

011 :

100 : 4ms

101 : 8ms

110 : 16ms

111 : 16ms

PSV1

PSV0

03h

[1:0]

Power Save Mode Control

These bits control whether the device is permitted to enter power save when input, output,

and load conditions dictate. If permitted to enter power save, they also control what mode of

power save the part can enter.

00 : PSAVE is disabled

01 : PSAVE enabled (low I

10 : UPSAVE enabled (ultrasonic mode)

11 : PSAVE is disabled

Definition of Registers and Bits (continued)