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VSC056

Data Sheet

Revision 4.1

January 2008

2.3

I/O Logic

Each general-purpose 5-V tolerant I/O pin is controlled by a set of registers in the Control register block.

The I/O supports a high current drive output buffer that can be configured as a totem pole or open-drain

driver. The input section of the I/O supports TTL signaling and includes an internal weak pull-up device.

This allows unused I/O pins to be left unconnected without high-current drain issues. The port bypass

control I/O pins, which are shared with Port 3, Port 4, Port 5, and Port 6, are generated using the same

buffer logic as the other ports. When enabled in Port Bypass Control mode, internal logic overrides the

existing configuration, with each I/O pin dedicated to the specific port bypass function. All I/O lines

default as inputs with the weak internal pull-up enabled.

2.4

Clock Generator

Clock generation for the device is composed of an internal oscillator, divider circuits, and a distribution

network. It supports nominal clock frequencies of:

●

8.0 MHz

●

8.33 MHz

●

8.854 MHz

●

10.0 MHz

●

33.33 MHz

●

40.0 MHz

●

50.0 MHz

●

53.125 MHz

The three CKSEL inputs select one of the eight available fixed clock frequencies. The internal low-

frequency clock (8.0 MHz to 12.5 MHz) is used for filtering incoming serial interface signals and interrupt

sources, as well as for clocking the slave state machine. Divided clocks provide the source for LED flash

rate generators. The oscillator provides a stable clock source for the device and requires the use of an off-

chip crystal with a frequency of 8.0 MHz, 8.33 MHz, 8.854 MHz, or 10.0 MHz and related passive

components or external clock source. The available fixed clock rates have been selected to allow the use of

other system clocks which may be available as well as low-cost crystals.

The following table describes the CKSEL settings for the available fixed input clocks and the associated

divider value.

Table 1. CKSEL Settings

CKSEL2

CKSEL1

CKSEL0

Input Clock

Divider

Internal Clock

VSS

10.0 MHz

N/A

10.0 MHz

VSS

VDD

8.33 MHz

N/A

8.33 MHz

VSS

VDD

VSS

8.854 MHz

N/A

8.854 MHz

VSS

VDD

8.0 MHz

N/A

8.0 MHz

VDD

VSS

40.0 MHz

÷4

10.0 MHz

VDD

VSS

VDD

33.33 MHz

÷4

8.33 MHz

VDD

VSS

53.125 MHz

÷6

8.854 MHz

VDD

50.0 MHz

÷6

8.33 MHz

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