80333 datasheet(67/75 Pages) INTEL

67 / 75 page

80333

Datasheet

Intel® 80333 I/O Processor Datasheet

May 2005

Order Number: 305433, Revision: 002

4.4.7

PCI Express* Differential Receiver (Rx) Input Specifications

Table 35.

PCI Express* Rx Input Specifications

Symbol

Parameter

Min.

Nom.

Max.

Units

Notes

VDIFFp-p

Differential input voltage

0.175

1.200

JTOTAL

Total Output Jitter.

0.65

VCM-AC

AC Common Mode

100

TReye

Receiver eye opening.

0.35

RL-DiffRX

Differential Return Loss

RL-CMTX

Common Mode Return Loss

ZRX-OUT-DC

DC Differential Output Impedance

100

110

Ω

ZRX-Match-DC

D+/D- impedance matching

-5

VRX-SQUELCH

Squelch detect threshold

175

CinRX

AC coupled

400

LSKEW-RX

Lane to Lane Skew at Rx

Notes:

Peak-Peak differential voltage. VDIFFp-p = 2 × VRMAx. Measured at the package pins of the receiver.

See Figure 20, “Transmitter Eye Diagram” on page 75.

Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver

device. A receiver must therefore tolerate any additional jitter generated by the package to the die.

Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg).

See Figure 21, “Receiver Eye Opening (Differential)” on page 75.

50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than

or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency

range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels.

The reference impedance for return loss measurements is 100

Ω for differential return loss and 25 Ωs

for common mode (i.e., as measured by a Vector Network Analyzer with 100

Ω differential probes).

Note this is based on a nominal PCI Express* interconnect differential characteristic impedance of

100

Ω. Applicable during active (L0) and Align states only.

DC Differential Mode Impedance 100

Ω ±10% tolerance.

DC impedance matching between two lanes of a port.

Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will

indicate a squelch condition.

All receivers shall be AC coupled to the media.

10.

Lane skew at the Receiver that must be tolerated.

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