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80333 Datasheet(PDF) 59 Page - Intel Corporation

Part # 80333
Description  I/O Processor
PDF  75 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

80333 Datasheet(HTML) 59 Page - Intel Corporation

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80333
Datasheet
Intel® 80333 I/O Processor Datasheet
May 2005
Order Number: 305433, Revision: 002
59
4.4
Targeted AC Specifications
4.4.1
Clock Signal Timings
Table 25.
PCI Clock Timings
Symbol
Parameter
PCI-X 133
PCI-X 100
PCI-X 66
PCI 66
PCI 33
Units
Notes
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Min.
Max
TF1
PCI clock Frequency
100
133
66
100
50
66
33
66
16
33
MHz
1
TC1
PCI clock Cycle Time - Avg.
Absolute Minimum
7.5
1010
151520
15
30
30
60
ns
1
7.375
9.875
14.8
14.8
29.7
ns
3,4
TCH1
PCI clock High Time
3
3
6
6
11
ns
TCL1
PCI clock Low Time
3
3
6
6
11
ns
TSR1
PCI clock Slew Rate
1.5
4
1.5
4
1.5
4
1.5
4
1
4
V/ns
2
PCI Spread Spectrum Requirements
fmod
PCI clock modulation
frequency
30
33
30
33
30
33
30
33
KHz
fspread
PCI clock frequency spread
-1
0
-1
0
-1
0
-1
0
%
Notes:
1.
Clock frequency may not change beyond spread-spectrum limits except while RSTIN# is asserted or PWRGD
deasserted.
2.
This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.
3.
The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
4.
Clock jitter class 2, per PCI-X Electrical and Mechanical Rev 2.0a specification
Table 26.
DDR Clock Timings
Symbol
Parameter
DDR-II 400
DDR333
Units
Notes
Minimum
Maximum
Minimum
Maximum
TF2
DDR SDRAM clock Frequency
200
167
MHz
TC2
DDR SDRAM clock Cycle Time
5.0
6.0/7.5(1)
ns
TCH2
DDR SDRAM clock High Time
2.15
2.7/3.37(1)
ns
TCL2
DDR SDRAM clock LowTime
2.15
2.7/3.37(1)
ns
TCS2
DDR SDRAM clock Period Stability
350
350
ps
Tskew2
DDR SDRAM clock skew for any differential
clock pair (M_CK[2:0] - M_CK[2:0]#)
100
100
ps
Tskew3
DDR SDRAM clock skew for any clock pair
and any system memory strobe (M_CK -
DQS).
-285
285
-285
285
ps
2
Notes:
1.
CL = 2.5/2.0.
2.
This specification applies for writes only; that is, when the 80333 is driving the strobes as well as the clocks. Refer to the
JEDEC specification for an explanation of strobe to clock timing for DDR reads.



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