80333 datasheet(32/75 Pages) INTEL

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80333

May 2005

Intel® 80333 I/O Processor Datasheet

Datasheet

Order Number: 305433, Revision: 002

Table 16.

Pin Mode Behavior (Sheet 1 of 4)

Reset

Norm

ECC

Off

32-Bit

DDR

32-Bit

B_PCI

32-Bit

A_PCI

M_CK[2:0]

M_CK[2:0]#

M_RST#

VOVOVO

MA[13:0]

0†

BA[1:0]

0†

RAS#

1†

CAS#

1†

WE#

1†

CS[1:0]#

1†

CKE[1:0]

0†

DQ[63:32]

Z†

ID,Z

DQ[31:0]

Z†

CB[7:0]

Z†

DQS[8]

Z†

ID,Z

DQS[7:4]

Z†

ID,Z

DQS[3:0]

Z†

DQS[8]#

Z†

ID,Z

DQS[7:4]#

Z†

ID,Z

DQS[3:0]#

Z†

DM[8]

Z†

DM[7:4]

Z†

DM[3:0]

Z†

DDR_VREF

ODT[1:0]2

VOVOVO

DDRRES[2:1]

Z†

DDRCRES0

DDRSLWCRES

DDRIMPCRES

A[22:16]

----

AD[15:0]

----

A[2:0]

----

ALE

----

Notes:

1 = driven to VCC

0 = driven to VSS

X = driven to unknown state

ID = the input is disabled

H = pulled up to VCC

PD = pull-up disabled

AO = analog output level

L = pulled down to VSS

Z = output disabled (floats)

VB = acts like a Valid Bidirectional pin

VO = a Valid Output level is driven

VI = Need to drive a Valid Input level

† = After power fail sequence completes

‡ = Caused by Hi-Z from mode pins only

Clocks become valid right before M_RST# deasserts.

ODT signal to be low during power up and initialization per DDR-II JEDEC specification.

High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.

Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.

Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

PWRGD.)

80333 Datasheet(PDF) 32 Page - Intel Corporation

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