80333 datasheet(28/75 Pages) INTEL

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80333

May 2005

Intel® 80333 I/O Processor Datasheet

Datasheet

Order Number: 305433, Revision: 002

Table 13.

Test and Miscellaneous Signals

Name

Count

Type

Description

TCK

Test Clock provides clock input for IEEE 1149.1 Boundary Scan

Testing (JTAG). State information and data are clocked into the

device on the rising clock edge and data is clocked out on the falling

clock edge.

TDI

Sync(T)

Test Data Input is the JTAG serial input pin. TDI is sampled on the

rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of

the Test Access Port. This signal has a weak internal pull-up to

ensure proper operation when this pin is not being driven.

TDO

Sync(T)

Rst(T)

Test Data Output is the serial output pin for the JTAG feature. TDO

is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-

DR states of the Test Access Port. At other times, TDO floats. The

behavior of TDO is independent of RSTIN# or PWRGD.

TRST#

Async

Test Reset asynchronously resets the Test Access Port controller

function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has

a weak internal pull-up.

TMS

Sync(T)

Test Mode Select is sampled on the rising edge of TCK to select

the operation of the test logic for IEEE 1149 Boundary Scan testing.

This pin has a weak internal pull-up.

N/C

No Connect. Do not connect to any signal, power or ground.

PWRDELAY

Async

Power Fail Delay is used to delay the reset of the memory

controller in a power-fail condition. This allows the self-refresh

command to be sent to the DDR SDRAM array.

PWRGD

Async

Power Supply Good: Signal that specifies that the motherboard

power supply has stabilized. This signal is used to asynchronously

reset the 80333 when it is low. The low period of this signal must be

long enough for the system power supply to stabilize and for the

base PLLs to lock.

Note:

This is the same signal as PERST# which is described in

the PCI Express* Card Electromechanical Specification,

Revision 1.0a.

RSTIN#

Async

Reset Input brings PCI-specific registers, sequencers, and signals

to a consistent state. When RSTIN# is asserted:

•

PCI output signals are driven to a known consistent state.

•

PCI bus interface output signals are three-stated.

•

Open drain signals such as B_SERR# are floated.

RSTIN# may be asynchronous to B_CLKIN when asserted or

deasserted. Although asynchronous, deassertion must be ensured

to be a clean, bounce-free edge.

Total

80333 Datasheet(PDF) 28 Page - Intel Corporation

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