80333 datasheet(22/75 Pages) INTEL

22 / 75 page

80333

May 2005

Intel® 80333 I/O Processor Datasheet

Datasheet

Order Number: 305433, Revision: 002

Table 8.

A PCI (IOP) Bus Signals (Sheet 1 of 2)

Name

Count

Type

Description

A_AD[31:0]

I/O

Sync(A)

Rst(A)

A PCI Address/Data is the multiplexed PCI address and lower 32

bits of the data bus.

A_AD[63:32]

I/O

Sync(A)

Rst(A)

A PCI Address/Data is the upper 32 bits of the PCI data bus.

A_PAR

I/O

Sync(A)

Rst(A)

A PCI Bus Parity is even parity across A_AD[31:0] and

A_C/BE[3:0]#.

A_PAR64

I/O

Sync(A)

Rst(A)

A PCI Bus Upper DWORD Parity is even parity across

A_AD[63:32] and A_C/BE[7:4]#.

A_C/BE[3:0]#

I/O

Sync(A)

Rst(A)

A PCI Bus Command and Byte Enables are multiplexed on the

same PCI pins. During the address phase, they define the bus

command. During the data phase, they are used as the byte

enables for A_AD[31:0].

A_C/BE[7:4]#

I/O

Sync(A)

Rst(A)

A PCI Byte Enables are used as byte enables for A_AD[63:32]

during secondary PCI data phases.

A_REQ64#

I/O

Sync(A)

Rst(A)

A PCI Bus Request 64-Bit Transfer indicates the attempt of a

64-bit transaction on the secondary PCI bus. When the target is

64-bit capable, the target acknowledges the attempt with the

assertion of A_ACK64#.

A_ACK64#

I/O

Sync(A)

Rst(A)

A PCI Bus Acknowledge 64-Bit Transfer indicates that the

device has positively decoded its address as the target of the

current access, indicates the target is willing to transfer data using

64 bits.

A_FRAME#

I/O

Sync(A)

Rst(A)

A PCI Bus Cycle Frame is asserted to indicate the beginning and

duration of an access.

A_IRDY#

I/O

Sync(A)

Rst(A)

A PCI Bus Initiator Ready indicates the initiating agent’s ability

to complete the current data phase of the transaction. During a

write, it indicates that valid data is present on the secondary

Address/Data bus. During a read, it indicates the processor is

ready to accept the data.

A_TRDY#

I/O

Sync(A)

Rst(A)

A PCI Bus Target Ready indicates the target agent’s ability to

complete the current data phase of the transaction. During a read,

it indicates that valid data is present on the secondary

Address/Data bus. During a write, it indicates the target is ready

to accept the data.

A_STOP#

I/O

Sync(A)

Rst(A)

A PCI Bus Stop indicates a request to stop the current

transaction on the secondary PCI bus.

A_DEVSEL#

I/O

Sync(A)

Rst(A)

A PCI Bus Device Select is driven by a target agent that has

successfully decoded the address. As an input, it indicates

whether or not an agent has been selected.

A_SERR#

I/O

Sync(A)

Rst(A)

A PCI Bus System Error is driven for address parity errors on

the secondary PCI bus.

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