80333 datasheet(64/75 Pages) INTEL

64 / 75 page

80333

May 2005

Intel® 80333 I/O Processor Datasheet

Datasheet

Order Number: 305433, Revision: 002

Table 31.

PCI Signal Timings

Symbol

Parameter

PCI-X 133

PCI-X 100

PCI-X 66

PCI 66

PCI 33

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TOV1

Clock to Output Valid

Delay for bused

signals

0.7

3.8

0.7

3.8

(1,2,3)

TOV2

Clock to Output Valid

Delay for point to point

signals

0.7

3.8

0.7

3.8

(1,2,3)

TOF

Clock to Output Float

Delay

(1,7)

TIS1

Input Setup to clock

for bused signals

1.2

1.7

(3,4,8)

TIS2

Input Setup to clock

for point to point

signals

1.2

1.7

10,

(3,4)

TIH1

Input Hold time from

clock

0.5

(4)

TRST

Reset Active Time

TRF

Reset Active to output

float delay

(5,6)

TIS3

REQ64# to Reset

setup time

clocks

TIH2

Reset to REQ64# hold

time

TIS4

PCI-X initialization

pattern to Reset setup

time

clocks

TIH3

Reset to PCI-X

initialization pattern

hold time

050

Notes:

See the timing measurement conditions in; Figure 7, “Output Timing Measurement Waveforms” on

page 69.

See Figure 16, “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 73, Figure 17, “PCI/PCI-X

TOV(max) Falling Edge AC Test Load” on page 74, and Figure 18, “PCI/PCI-X TOV(min) AC Test

Load” on page 74.

Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused.

See the timing measurement conditions in Figure 8, “Input Timing Measurement Waveforms” on

page 70.

RST# is asserted and deasserted asynchronously with respect to CLK.

All output drivers must be floated when RST# is active.

For purposes of Active/Float timing measurements, the HI-Z or ‘off’ state is defined to be when the

total current delivered through the component pin is less than or equal to the leakage current

specification.

Setup time applies only when the device is not driving the pin. Devices cannot drive and receive

signals at the same time.

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