80333 datasheet(63/75 Pages) INTEL

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80333

Datasheet

Intel® 80333 I/O Processor Datasheet

May 2005

Order Number: 305433, Revision: 002

4.4.3

Peripheral Bus Interface Signal Timings

Table 30.

Peripheral Bus Signal Timings

Symbol

Parameter

Min.

Max.

Units

Notes

TOV1

Output Valid Delay from M_CK

(1, 3)

TOF

Output Float Delay from M_CK

(1, 3)

TIS1

Input Setup to M_CK

4.5

(2)

TIH1

Input Hold from M_CK

(2)

TAH1

ALE High time

TAV1

ALE high to address Valid

TAH2

ALE low to address invalid

TAS1

Address valid to ALE low

TAO1

ALE low to POE# low

TAW1

ALE low to PWE# low

TAH3

PWE# high to Data Invalid

TAS2

Data valid to PWE# high

TAC1

ALE low to PCE[1:0]# low

Notes:

See Figure 7, “Output Timing Measurement Waveforms” on page 69.

See Figure 8, “Input Timing Measurement Waveforms” on page 70.

See Figure 14, “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 73.

See Table 32, AC Measurement Conditions.

All timing referenced to M_CK is for functional testing, for the cases where M_CK × N = IBCLK.

PBI Clock is internal only; 66 MHz with 333 MHz internal bus.

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