80333 datasheet(4/75 Pages) INTEL

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80333

July 2005

Intel® 80333 I/O Processor Datasheet

Datasheet

Order Number: 305433, Revision: 003US

3Intel® 80333 I/O Processor Signal Group Locations (Bottom View) ........................................... 38

4Intel® 80333 I/O Processor Ballout — Left Side (Bottom View) ................................................. 39

5Intel® 80333 I/O Processor Ballout — Right Side (Bottom View) ............................................... 40

Clock Timing Measurement Waveforms..................................................................................... 69

Output Timing Measurement Waveforms ................................................................................... 69

Input Timing Measurement Waveforms...................................................................................... 70

9I2C/SMBus Interface Signal Timings .......................................................................................... 70

UART Transmitter Receiver Timing............................................................................................ 70

DDR SDRAM Write Timings .......................................................................................................71

DDR SDRAM Read Timings....................................................................................................... 71

Write PreAmble/PostAmble Durations........................................................................................ 72

AC Test Load for All Signals Except PCI and DDR SDRAM ...................................................... 73

AC Test Load for DDR SDRAM Signals ..................................................................................... 73

PCI/PCI-X TOV(max) Rising Edge AC Test Load ...................................................................... 73

PCI/PCI-X TOV(max) Falling Edge AC Test Load ..................................................................... 74

PCI/PCI-X TOV(min) AC Test Load ........................................................................................... 74

Transmitter Test Load (100

Ω differential load).......................................................................... 74

Transmitter Eye Diagram............................................................................................................ 75

Receiver Eye Opening (Differential) ...........................................................................................75

Tables

Pin Description Nomenclature .................................................................................................... 15

DDR SDRAM Signals ................................................................................................................. 16

MISC SDRAM Signals ................................................................................................................ 17

DDR-II SDRAM Signals .............................................................................................................. 17

Peripheral Bus Interface Signals ................................................................................................ 18

PCI Express* Signals ................................................................................................................. 19

B PCI (Slot Expansion) Bus Signals ........................................................................................... 20

A PCI (IOP) Bus Signals............................................................................................................. 22

I2C/SMBus Signals ..................................................................................................................... 24

Interrupt Signals ......................................................................................................................... 24

Hot-Plug Controller Signals for Parallel 1-slot, No-Glue ............................................................. 25

UART Signals ............................................................................................................................. 26

Test and Miscellaneous Signals ................................................................................................. 28

Reset Strap Signals .................................................................................................................... 29

Power and Ground Pins ............................................................................................................. 31

Pin Mode Behavior ..................................................................................................................... 32

Pin Multiplexing for Functional Modes ........................................................................................ 36

FC-style, H-PBGA Package Dimensions.................................................................................... 37

829-Lead Package — Alphabetical Ball Listings ........................................................................ 41

829-Lead Package — Alphabetical Signal Listings .................................................................... 48

Absolute Maximum Ratings ........................................................................................................ 56

Operating Conditions .................................................................................................................. 56

DC Characteristics...................................................................................................................... 57

ICC Characteristics...................................................................................................................... 58

PCI Clock Timings ...................................................................................................................... 59

DDR Clock Timings .................................................................................................................... 59

PCI Express* Clock Timings....................................................................................................... 60

DDR SDRAM Signal Timings ..................................................................................................... 61

80333 Datasheet(PDF) 4 Page - Intel Corporation

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