R26 datasheet(83/487 Pages) RENESAS

83 / 487 page

R8C/26 Group, R8C/27 Group

7. Programmable I/O Ports

Rev.2.10

Sep 26, 2008

Page 64 of 453

REJ09B0278-0210

Figure 7.12

Registers PUR0 and PUR1

Figure 7.13

P1DRR Register

Pull-Up Control Register 0

Symbol

Address

After Reset

PUR0

00FCh

00h

Bit Symbol

Bit Name

Function

NOTE:

—

(b5-b4)

PU02

Set to 0. When read, the content is 0.

0 : Not pulled up

1 : Pulled up

Reserved bits

0 : Not pulled up

1 : Pulled up

When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.

PU07

P3_4 to P3_7 pull-up(1)

PU06

P3_1 and P3_3 pull-up(1)

b3 b2 b1 b0

PU00

b7 b6 b5 b4

P0_4 to P0_7 pull-up(1)

P0_0 to P0_3 pull-up(1)

PU03

P1_4 to P1_7 pull-up(1)

P1_0 to P1_3 pull-up(1)

PU01

Pull-Up Control Register 1

Symbol

Address

After Reset

PUR1

00FDh

00h

Bit Symbol

Bit Name

Function

NOTE:

PU13

P5_4 pull-up(1)

0 : Not pulled up

1 : Pulled up

—

(b5-b4)

Reserved bits

PU11

P4_5 pull-up(1)

PU12

Set to 0. When read, the content is 0.

—

(b7-b6)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

(b0)

Reserved bit

Set to 0. When read, the content is 0.

P5_3 pull-up(1)

b7 b6 b5 b4

—

When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.

b3 b2 b1

Port P1 Drive Capacity Control Register (For N, D Version Only)

Symbol

Address

After Reset

P1DRR

00FEh

00h

Bit Symbol

Bit Name

Function

NOTE:

P1DRR4

P1_4 drive capacity

P1_5 drive capacity

P1_1 drive capacity

P1_0 drive capacity

P1DRR3

P1_2 drive capacity

P1DRR1

P1DRR0

b7 b6 b5 b4 b3 b2 b1

Both “H” and “L” output are set to high drive capacity.

P1DRR7

P1DRR5

Set P1 output transistor drive capacity

0 : Low

1 : High(1)

P1DRR2

P1_7 drive capacity

P1_3 drive capacity

P1DRR6

P1_6 drive capacity

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