R26 datasheet(91/487 Pages) RENESAS

91 / 487 page

R8C/26 Group, R8C/27 Group

7. Programmable I/O Ports

Rev.2.10

Sep 26, 2008

Page 72 of 453

REJ09B0278-0210

X: 0 or 1

NOTES:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Set the INT1SEL bit in the PMR register to 1 (P3_6).

3. Set bits UART1SEL1 and UART1SEL0 in the PINSR1 register to 10b.

4. N-channel open drain output by setting the NCH bit in the U1C0 register to 1.

X: 0 or 1

NOTES:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Set the SSISEL bit in the PMR register to 0 (P3_3).

3. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open drain output).

4. N-channel open drain output by setting the NCH bit in the U1C0 register to 1.

Table 7.30

Port P3_6/(TXD1)/(RXD1)/(INT1)

PD3

PMR

U1MR

INTEN

Function

Bit

PD3_6

TXD1EN

SMD2

SMD1

SMD0

INT1EN

Setting

value

Input port(1)

0000

Output port

0000

INT1 input(1, 2)

0001

0010

TXD1 output(3, 4)

1000

1010

1100

RXD1 input(1)

Table 7.31

Port P3_7/TRAO/SSO/RXD1/(TXD1)

PD3

PMR

Clock Synchronous Serial I/O with Chip

Select (Refer to Table 16.4

Association between

Communication Modes and I/O Pins.)

TRAMR

UART1 setting

Function(3)

Bit

PD3_7

IICSEL

SSO output control

SSO input control

TOENA

−

Setting

value

Other than TXD1, RXD1

usage conditions

Input port(1)

Other than TXD1, RXD1

usage conditions

Output port

Refer to Table 7.32 Port

P3_7 UART1 Setting

Condition

TXD1 output(4)

Refer to Table 7.32 Port

P3_7 UART1 Setting

Condition

RXD1 input(1)

Other than TXD1, RXD1

usage conditions

TRAO output

Other than TXD1, RXD1

usage conditions

SSO output(2)

Other than TXD1, RXD1

usage conditions

SSO input(2)

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