UBA2071ATS datasheet(15/35 Pages) NXP

15 / 35 page

UBA2071_A_1

Product data sheet

Rev. 01 — 23 June 2008

15 of 35

NXP Semiconductors

UBA2071; UBA2071A

Half bridge control IC for CCFL backlighting

Under normal operating conditions, the voltage across capacitor C2, which is connected

to the CVFB pin, will follow the voltage on the CIFB pin. During the lamps-on period of the

PWM dimming, the voltage across C3, which is connected to the CSWP pin, will follow the

voltage on the CVFB pin and therefore also the voltage on the CIFB pin.

The voltage on the CSWP pin is connected to the VCO input of the HF oscillator and thus

controls the switching frequency. If the load is assumed to be inductive an increase in the

frequency will cause a decrease in the lamp current, while a decrease in the frequency will

cause an increase in the lamp current.

The advantage of having a separate current regulation loop timing capacitor pin CIFB next

to the voltage regulation loop timing capacitor CVFB is that time constants for both loops

can be set independently. The separate PWM dimming sweep timing capacitor pin CSWP

makes it possible to set the PWM dimming sweep speed independent of the current and

voltage regulation loops.

8.11 PWM dimming

Pulse Width Modulation (PWM) dimming is a method of reducing the average lamp light

output by switching the lamps on and off with a repetition rate or PWM frequency, fPWM,

high enough not to be seen by the human eye (but much lower than the inverter frequency

fsw). By varying the lamp-on to lamp-off, period ratio, called the duty cycle δPWM, the light

output can be varied over a wide range.

The voltage at the CSWP pin determines the actual switching frequency, it inverses in

proportion to the switching frequency. During the lamps-on period of the PWM dimming it

follows the voltage at the CVFB pin (the current Ich(CSWP) is drained by the tracking circuit

between the CVFB pin and the CSWP pin).

Just prior to transitioning towards the lamps-off period of the PWM dimming the lamp

current control loop, see Figure 11, is opened by opening switches S1. The voltage on the

CSWP pin is swept down, decaying the lamp current, leading in the PWM lamp-off

situation, after which the half bridge switch actions are stopped, resulting in true zero lamp

current. see Figure 9. In the meantime the regulation level is preserved in C1 and C2. The

Fig 11. Lamp frequency control circuit

to CCFLs

DSR

Vref(creg)

Ich(CSWP)

PWMD

Idch(CSWP)

to VCO

Ich(CVFB)

CIFB

CVFB

CSWP

UBA2071

OTA

014aaa106

IFB

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