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ADL5502

Rev. A | Page 23 of 28

The device is placed in peak-hold mode by placing the switch

SW2 in the position closes to the SW2 label. Envelope-tracking

mode is possible by setting SW2 in the opposite switch position

(away from the SW2 label). A signal generator can drive the control

mode via the SMA labeled CNTL (see Table 4 for more details).

EVALUATION BOARD

Figure 65 shows the schematic of the ADL5502 evaluation board.

The board is powered by a single supply in the 2.5 V to 3.3 V

range. The power supply is decoupled by 100 pF and 0.1 μF

capacitors.

Operating in Peak-Hold Mode

Table 4 details the various configuration options of the evaluation

board. Figure 66 and Figure 67 show the component and circuit

layouts of the evaluation board.

To operate the device in peak-hold mode, the control line must be

temporally set to high (reset mode for >1 μs) and then set back to

low (peak-hold mode). This allows the ADL5502 initialize to a

known state.

The RF input has a broadband match of 50 Ω using a single

75 Ω resistor at R10. More precise matching at spot frequencies

is possible using the pads for C15, C16, and R10 (see the RF

Input Interfacing section).

Land Pattern and Soldering Information

Pad diameters of 0.28 mm are recommended with a solder paste

mask opening of 0.38 mm. For the RF input trace, a trace width

of 0.30 mm is used, which corresponds to a 50 Ω characteristic

impedance for the dielectric material being used (FR4). All traces

going to the pads are tapered down to 0.15 mm. For the RFIN

line, the length of the tapered section is 0.20 mm.

The two outputs, accessible via the SMAs labeled VRMS and

VENV, provide the rms response and the envelope/peak-hold

measurement of the RF input power level. The device must be

enabled by switching SW1 to high (setting the switch to the

position opposite that of the SW1 label).

ADL5502

FLTR

VPOS

RFIN

VRMS

PEAK

CNTL

C14

100pF

C13

0.1µF

ENBL

COMM

C12

100pF

C11

0.1µF

ENBL

VPOS

SW1

VPOS

(P1 – 1)

(P1 – 4)

VRMS

0Ω

(P1 – 8)

VPOS

RFIN

R10

75Ω

0Ω

C15

C16

VPOS

C18

(OPEN)

R11

(OPEN)

0Ω

C19

(OPEN)

R12

(OPEN)

VENV

CNTL

0Ω

(P1 – 6)

0Ω

R13

0Ω

10kΩ

SW2

10kΩ

C20

(OPEN)

(P1 – 6)

0Ω

C17

10nF

Figure 65. Evaluation Board Schematic

Figure 66. Layout of Evaluation Board, Component Side

Figure 67. Layout of Evaluation Board, Circuit Side

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