ADP5042 datasheet(26/32 Pages) AD

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ADP5042

Rev. 0 | Page 26 of 32

using a slightly longer watchdog timeout. In the program that

calls the subroutine, WDI1 is set high. The subroutine sets

WDI1 low when it is called. If the program executes without error,

WDI1 is toggled high and low with every loop of the program.

If the subroutine enters an infinite loop, WDI1 is kept low, the

watchdog times out, and the microprocessor is reset (see

Figure 65).

START

SET WDI

HIGH

PROGRAM

CODE

SUBROUTINE

SET WDI

LOW

RETURN

INFINITE LOOP:

WATCHDOG

TIMES OUT

RESET

Figure 65. Watchdog Flow Diagram

The second watchdog, refreshed through the WDI2 pin, is

useful in applications where safety is a very critical factor and

the system must recover from unwanted operations, for example, a

processor stuck in a continuous loop where Watchdog 1 is kept

refreshed or environmental conditions that may unset or damage

the processor port controlling the WDI1 pin. In the event of a

Watchdog 2 timeout, the ADP5042 power cycles all the supplied

rails to guarantee a clean processor start.

ADP5042

MICROPROCESSOR

VCC

VOUT1

VOUT2

nRSTO

WDI1

RESET

WDI2

VIN1

I/O

VCORE

VDDIO

Figure 66. Typical Applications Circuit

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5042 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

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