SC662 datasheet(19/30 Pages) SEMTECH

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SC662

PCB Layout Considerations

Following fundamental layout rules is critical for achieving

the performance specified in the Electrical Characteristics

table. A recommended layout is illustrated in Figures 8, 9,

and 10. Figure 8 shows a composite view of the two

copper layers plus components, vias, and text descriptors.

Figure 9 shows the copper layer on the component side of

the board, and Figure 10 is the copper layer for ground

and routing.

The following guidelines are recommended when devel-

oping a PCB layout:

Place all capacitors (C1, C2, CIN, and COUT) as

close to the device as possible, and on the same

side of the board as the SC662.

CIN, COUT should have their grounds connected

at one point as shown in Figure 8, with multiple

vias to ground.

C1 and C2 should be placed so that they do not

require vias to connect to the SC662.

All charge pump current passes through pins IN,

OUT, C1-, C1+, C2+, and C2-. Ensure that all con-

nections to these pins use wide traces. Layout

should minimize the resistance and inductance

of these traces.

Make all ground connections to a ground plane

as shown in the example layout. There should

be a short unobstructed path between all

ground vias on the ground plane.

The power trace connecting the battery to the

IN pin should be sized for 300mA of battery

current. The power trace should be on a layer

adjacent to the ground return. If possible, make

the power trace equal in width to the ground

return trace.

The output trace connecting the OUT pin to the

anode terminals of the LEDs should be sized for

150mA of DC current.

Up to six LED traces connect between the LED

cathodes and the BLn pins. Each LED trace width

should be sized for 25mA of DC current. The LED

traces route in parallel on one layer and serve as

•

the return current path from the LEDs to the BLn

pins.

Figure 8 is representative of a two layer design.

As shown in this figure, the OUT trace can be

placed next to the six LED traces on the same

layer. However, if more than two layers are avail-

able, the preferred method is to have the OUT

trace route underneath the LED traces on a dif-

ferent layer.

Double vias are preferred for grounding pin 3 of

the SC662, and also for grounding the ground

leads of CIN and COUT.

The SPIF trace should be routed away from

sources of noise to preserve the signal integrity

for the SemPulse interface.

Multiple vias are recommended for the thermal

pad at the center of the device.

SC662

Ground Layer

Vias to

ground

plane

CIN

BL6

SPIF

GND

C1-

C2-

C2+

C1+

BL1

BL2

BL3

BL4

BL5

OUT

COUT

OUT to LED Anodes

Positive from battery

Ground return to battery

To LED1

To LED2

To LED3

To LED4

To LED5

To LED6

To SPIF output

Figure 8 — Recommended PCB Layout

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Applications Information (continued)

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