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PIC12F752 Datasheet(PDF) 171 Page - Microchip Technology |
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PIC12F752 Datasheet(HTML) 171 Page - Microchip Technology |
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171 / 204 page ![]() 2011 Microchip Technology Inc. Preliminary DS41576A-page 171 PIC12F752/HV752 Capacitive Loading Specs on D101* CIO All I/O pins — — 50 pF Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C TA +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C TA +125°C D131 VPR VDD for Read VMIN —5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Bulk Erase/Write 4.5 — 5.5 V D132A VPEW VDD for Row Erase/Write VMIN —5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated 20.8 DC Characteristics: PIC12F752/HV752-I (Industrial) PIC12F752/HV752-E (Extended) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: This specification applies to RA3/MCLR configured as RA3 with the internal weak pull-up disabled. 4: This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is configured as MCLR Reset pin, the weak pull-up is always enabled. |
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