CYUSB3014 datasheet(16/38 Pages) CYPRESS

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PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H

Page 16 of 38

AC Timing Parameters

GPIF II Timing

Figure 7. GPIF II Timing in Synchronous Mode

CTL(O UT)

CTL(IN)

tDH

tDS

tCLK

CLK

tCTLO

tCO E

Data(IN)

Data 1

(O UT)

tHZ

tLZ

tDO H

tCO H

tCLKH tCLKL

tLZ

Data 2

(O UT)

tCO

tDO H

DQ [31:0]

Note

3. All parameters guaranteed by design and validated through characterization.

Table 8. GPIF II Timing Parameters in Synchronous Mode[3]

Parameter

Description

Min

Max

Unit

Frequency

Interface clock frequency

–

100

MHz

tCLK

Interface clock period

–

tCLKH

Clock high time

–

tCLKL

Clock low time

–

CTL input to clock setup time

(Sync speed =1)

2–

CTL input to clock hold time

(Sync speed =1)

0.5

–

tDS

Data in to clock setup time

(Sync speed =1)

2–

tDH

Data in to clock hold time

(Sync speed =1)

0.5

–

tCO

Clock to data out propagation delay when DQ bus is already in

output direction(Sync speed =1)

–8

tCOE

Clock to data out propagation delay when DQ lines change to

output from tristate and valid data is available on the DQ bus

(Sync speed =1)

-9

tCTLO

Clock to CTL out propagation delay (Sync speed =1)

–

tDOH

Clock to data out hold

–

tCOH

Clock to CTL out hold

–

tHZ

Clock to High-Z

–

tLZ

Clock to Low-Z (Sync speed =1)

–

tS_ss0

CTL input/data input to clock setup time (Sync speed = 0)

–

tH_ss0

CTL input/data input to clock hold time (Sync speed = 0)

2.5

–

tCO_ss0

Clock to data out / CTL out

propagation delay (sync speed = 0)

–15

tLZ_ss0

Clock to low-Z (sync speed = 0)

–

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