CYUSB3014 datasheet(23/38 Pages) CYPRESS

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PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H

Page 23 of 38

Asynchronous Slave FIFO Timing

Figure 12. Asynchronous Slave FIFO Read Mode

Asynchronous Slave FIFO Read Sequence

Description

■ FIFO address is stable and the SLCS# signal is asserted.

■ SLOE# is asserted. This results in the data bus being driven.

■ SLRD # is asserted.

■ Data from the FIFO is driven on assertion of SLRD#. This data

is valid after a propagation delay of tRDO from the falling edge

of SLRD#.

■ FIFO pointer is incremented on de-assertion of SLRD#

In the above diagram , data N is the first valid data read from the

FIFO. For data to appear on the data bus during the read cycle

SLOE# must be in an asserted state. SLRD# and SLOE# can

also be tied together.

The same sequence of events is also shown for a burst read.

Note: In burst read mode, during SLOE# assertion, the data bus

is in a driven state (data driven is from previously addressed

FIFO). On assertion of SLRD# data from the FIFO is driven on

the data bus (SLOE# must also be asserted) and the FIFO

pointer is incremented on de-assertion of SLRD#.

FIFO ADDR

tAS

SLCS

SLRD

tRDl

SLOE

FLAGA

dedicated thread Flag for An

(1=Not empty 0 = Empty)

tOE

Data Out

High-Z

tAH

DN(An)

tRDO

tOE

tRDO

tOH

tRDh

tRDO

tLZ

DN(An)

DN(Am)

DN+1(Am)

DN+2(Am)

SLWR

(HIGH)

FLAGB

dedicated thread Flag for Am

(1=Not empty 0 = Empty)

tRFLG

tFLG

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