CYUSB3014 datasheet(25/38 Pages) CYPRESS

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PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H

Page 25 of 38

Asynchronous Slave FIFO Write Sequence

Description

■ FIFO address is driven and SLCS# is asserted

■ SLWR# is asserted. SLCS# must be asserted with SLWR# or

before SLWR# is asserted

■ Data must be present on the bus tWRS before the deasserting

edge of SLWR#

■ De-assertion of SLWR# causes the data to be written from the

data bus to the FIFO and then FIFO pointer is incremented

■ The FIFO flag is updated after the tWFLG from the de-asserting

edge of SLWR.

The same sequence of events is shown for a burst write.

Note that in the burst write mode, on SLWR# de-assertion, the

data is written to the FIFO and then the FIFO pointer is incre-

mented.

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device/processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines have to be held constant during the PKTEND#

assertion.

Zero Length Packet: The external device/processor can signal a

Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and address must

be driven as shown in the above timing diagram.

FLAG Usage: The FLAG signals are monitored by the external

processor for flow control. FLAG signals are outputs from

EZ-USB FX3 that may be configured to show empty/full/partial

status for a dedicated address or the current address.

Note

6. All parameters guaranteed by design and validated through characterization.

Table 11. Asynchronous Slave FIFO Parameters[6]

Parameter

Description

Min

Max

Units

tRDI

SLRD# low

–

tRDh

SLRD# high

–

tAS

Address to SLRD#/SLWR# setup time

–

tAH

SLRD#/SLWR#/PKTEND to address hold time

–

tRFLG

SLRD# to FLAGS output propagation delay

–

tFLG

ADDR to FLAGS output propagation delay

22.5

tRDO

SLRD# to data valid

–

tOE

OE# low to data valid

–

tLZ

OE# low to data low-Z

–

tOH

SLOE# deassert data output hhold

–

22.5

tWRI

SLWR# low

–

tWRh

SLWR# high

–

tWRS

Data to SLWR# setup time

–

tWRH

SLWR# to Data Hold time

–

tWFLG

SLWR#/PKTEND to Flags output propagation delay

–

tPEI

PKTEND low

7.5

–

tPEh

PKTEND high

7.5

–

tWRPE

SLWR# deassert to PKTEND deassert

–

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