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CYUSB3014 Datasheet(PDF) 27 Page - Cypress Semiconductor |
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CYUSB3014 Datasheet(HTML) 27 Page - Cypress Semiconductor |
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27 / 38 page  PRELIMINARY CYUSB3014 Document Number 001-52136 Rev. *H Page 27 of 38 Note 7. All parameters guaranteed by design and validated through characterization. Table 12. I2C Timing Parameters[7] Parameter Description Min Max Units Notes I2C Standard Mode Parameters fSCL SCL clock frequency 0 100 kHz tHD:STA Hold time START condition 4 – µs tLOW LOW period of the SCL 4.7 – µs tHIGH HIGH period of the SCL 4 – µs tSU:STA Setup time for a repeated START condition 4.7 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 250 – ns tr Rise time of both SDA and SCL signals – 1000 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 4 – µs tBUF Bus free time between a STOP and START condition 4.7 – µs tVD:DAT Data valid time – 3.45 µs tVD:ACK Data valid ACK – 3.45 µs tSP Pulse width of spikes that must be suppressed by input filter n/a n/a I2C Fast Mode Parameters fSCL SCL clock frequency 0 400 kHz tHD:STA Hold time START condition 0.6 – µs tLOW LOW period of the SCL 1.3 – µs tHIGH HIGH period of the SCL 0.6 – µs tSU:STA Setup time for a repeated START condition 0.6 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 100 – ns tr Rise time of both SDA and SCL signals – 300 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 0.6 – µs tBUF Bus free time between a STOP and START condition 1.3 – µs tVD:DAT Data valid time – 0.9 µs tVD:ACK Data valid ACK – 0.9 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V) fSCL SCL clock frequency 0 1000 kHz tHD:STA Hold time START condition 0.26 – µs tLOW LOW period of the SCL 0.5 – µs tHIGH HIGH period of the SCL 0.26 – µs tSU:STA Setup time for a repeated START condition 0.26 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 50 – ns tr Rise time of both SDA and SCL signals – 120 ns tf Fall time of both SDA and SCL signals – 120 ns tSU:STO Setup time for STOP condition 0.26 – µs tBUF Bus free time between a STOP and START condition 0.5 – µs tVD:DAT Data valid time – 0.45 µs tVD:ACK Data valid ACK – 0.45 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns [+] Feedback [+] Feedback |
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