CYUSB3014 datasheet(30/38 Pages) CYPRESS

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CYUSB3014

Document Number 001-52136 Rev. *H

Page 30 of 38

Reset Sequence

The hard reset sequence requirements for EZ-USB FX3 are specified here.

Notes

9. All parameters guaranteed by design and validated through characterization.

10. Depends on LAG and LEAD setting in SPI_CONFIG register.

Table 14. SPI Timing Parameters[9]

Parameter

Description

Min

Max

Units

fop

Operating frequency

MHz

tsck

Cycle time

–

twsck

Clock high/low time

13.5

–

tlead

SSN-SCK lead time

1/2 tsck[10]-5

1.5tsck[10]+ 5

tlag

Enable lag time

0.5

1.5 tsck[10]+5

trf

Rise/fall time

–

tsdd

Output SSN to valid data delay time

–

tdv

Output data valid time

–

tdi

Output data invalid

–

tssnh

Minimum SSN high time

–

tsdi

Data setup time input

–

thoi

Data hold time input

–

tdis

Disable data output on SSN high

–

Table 15. Reset and Standby Timing Parameters

Parameter

Definition

Conditions

Min (ms)

Max (ms)

tRPW

Minimum RESET# pulse width

Clock Input

–

Crystal Input

–

tRH

Minimum high on RESET#

–

tRR

Reset recovery time (after which Boot loader begins

firmware download)

–1

–

tSBY

Time to enter standby/suspend (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

––

tWU

Time to wakeup from standby

Clock Input

–

Crystal Input

–

tWH

Minimum time before Standby/Suspend source may

be reasserted

–5

–

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