LPC1850 datasheet(101/142 Pages) NXP

101 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

101 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

11.4 I2S-bus interface

[1]

CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) =

1600 ns, corresponds to the SCK signal in the I2S-bus specification.

Fig 30. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 13.

Dynamic characteristics: I2S-bus interface pins

Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>. Conditions and data refer to I2S0 and I2S1 pins.

Symbol

Parameter

Conditions

Min

Max

Unit

common to input and output

rise time

[1]

-<tbd>

fall time

[1]

-<tbd>

tWH

pulse width HIGH

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

[1]

<tbd>

tWL

pulse width LOW

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

[1]

-<tbd>

output

tv(Q)

data output valid time

on pin I2Sx_TX_SDA

[1]

-<tbd>

input

tsu(D)

data input set-up time

on pin I2Sx_RX_SDA

[1]

<tbd>

th(D)

data input hold time

on pin I2Sx_RX_SDA

[1]

<tbd>

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