LPC1850 datasheet(103/142 Pages) NXP

103 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

103 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

11.5 SSP interface

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2]

Tamb = 40 C to 85 C; VDD(REG)(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.

[3]

Tcy(clk) = 12  Tcy(PCLK).

[4]

Tamb = 25 C; VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V.

Table 14.

Dynamic characteristics: SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Max

Unit

Tcy(PCLK)

PCLK cycle time

<tbd>

Tcy(clk)

clock cycle time

full-duplex mode

[1]

<tbd>

when only

transmitting

<tbd>

SSP master

tDS

data set-up time

in SPI mode

[2]

<tbd>

Tcy(clk)

tDH

data hold time

in SPI mode

[2]

<tbd>

tv(Q)

data output valid time

in SPI mode

[2]

<tbd>

th(Q)

data output hold time

in SPI mode

[2]

<tbd>

SSP slave

tDS

data set-up time

in SPI mode

[3][4]

<tbd>

tDH

data hold time

in SPI mode

[3][4]

<tbd>

 T

cy(PCLK) +

<tbd>

-ns

tv(Q)

data output valid time

in SPI mode

[3][4]

-<tbd>

 T

cy(PCLK) +

<tbd>

th(Q)

data output hold time

in SPI mode

[3][4]

-<tbd>

 T

cy(PCLK) +

<tbd>

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