(e

+

NI

2

´

e

NO

2

G

´

6

V

DIFF

BW

INA826

SBOS562B

– AUGUST 2011 – REVISED DECEMBER 2011

www.ti.com

Resistor-adjustable INAs such as the INA826 show the lowest gain error in G = 1 because of the inherently

well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =

10 V/V or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the

resistor drift of the 24.7-k

Ω feedback resistors in conjunction with the external gain resistor. Except for very high

gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset

drift. The INA826 offers the lowest gain error over temperature in the marketplace for both G

> 1 and G = 1 (no

external gain resistor). Table 2 summarizes the major error sources in common INA applications and compares

the two cases of G = 1 (no external resistor) and G = 10 (5.49-k

Ω external resistor). As can be seen in Table 2,

while the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there

are much fewer drift errors because of the much lower gain error drift. In most applications, these static errors

can readily be removed during calibration in production. All calculations refer the error to the input for easy

comparison and system evaluation.

Table 2. Error Calculation

INA826

G = 10 ERROR

G = 1 ERROR

SPEC

ERROR SOURCE

ERROR CALCULATION

(ppm)

(ppm)

ABSOLUTE ACCURACY AT +25

°C

Input offset voltage (

μV)

150

150

150

Output offset voltage (

μV)

700

70

700

Input offset current (nA)

5

50

50

104 (G = 10),

CMRR (dB)

63

631

84 (G = 1)

Total absolute accuracy error (ppm)

333

1531

DRIFT TO +105

°C

35 (G = 10),

Gain drift (ppm/

°C)

GTC

2800

80

1 (G = 1)

Input offset voltage drift (

μV/°C)

2

160

160

Output offset voltage drift (

μV/°C)

10

80

800

Offset current drift (pA/

°C)

60

48

48

Total drift error (ppm)

3088

1088

RESOLUTION

Gain nonlinearity (ppm of FS)

5

5

5

Voltage noise (1 kHz)

10

10

Total resolution error (ppm)

15

15

TOTAL ERROR

Total error

Total error = sum of all error sources

3436

2634

LAYOUT GUIDELINES

Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed

circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.

Place 0.1-

μF bypass capacitors close to the supply pins. These guidelines should be applied throughout the

analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference

(EMI) susceptibility.

CMRR vs Frequency

The INA826 pinout has been optimized for achieving maximum CMRR performance over a wide range of

frequencies. However, care must be taken to ensure that both input paths are well-matched for source

impedance and capacitance to avoid converting common-mode signals into differential signals. In addition,

parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications

should be chosen so that the switch capacitance is as small as possible.

24

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