EM773 datasheet(14/51 Pages) PHILIPS

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EM773

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Product data sheet

Rev. 2 — 3 January 2012

14 of 51

NXP Semiconductors

EM773

Energy metering IC

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.14 Windowed WatchDog Timer

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.14.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in

multiples of Tcy(WDCLK)  4.

• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated

watchdog oscillator (WDO). This gives a wide range of potential timing choices of

watchdog operation under different power conditions.

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