EM773 datasheet(19/51 Pages) PHILIPS

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EM773

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Product data sheet

Rev. 2 — 3 January 2012

19 of 51

NXP Semiconductors

EM773

Energy metering IC

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the EM773 user manual.

7.16.5 APB interface

The APB peripherals are located on one APB bus.

7.16.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.16.1).

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

EM773 Datasheet(PDF) 19 Page - NXP Semiconductors