EM773 datasheet(18/51 Pages) PHILIPS

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EM773

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Product data sheet

Rev. 2 — 3 January 2012

18 of 51

NXP Semiconductors

EM773

Energy metering IC

7.16 System control

7.16.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 2 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.16.2 Reset

Reset has four sources on the EM773: the RESET pin, the Watchdog reset, Power-On

Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.16.3 Brownout detection

The EM773 includes four levels for monitoring the voltage on the VDD pin. If this voltage

falls below one of the four selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.16.4 Code security (Code Read Protection - CRP)

This feature of the EM773 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and

In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the EM773 user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

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