LPC1850 datasheet(123/157 Pages) PHILIPS

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LPC1850_30_20_10

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Preliminary data sheet

Rev. 3 — 6 December 2011

123 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

[1]

In the DAC CR register, bit BIAS = 0 (see the LPC18xx user manual).

[2]

Settling time is calculated within 1/2 LSB of the final value.

Rs < 1/((7  fclk(ADC)  Cia)  2 k

Fig 36. ADC interface to pins

LPC18xx

ADC0_n/ADC1_n

Cia = 2 pF

Rvsi

VSS

VEXT

002aag697

ADC

COMPARATOR

2 kΩ (analog pin)

2.2 kΩ (multiplexed pin)

Table 26.

DAC characteristics

VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

differential linearity error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

LSB

EL(adj)

integral non-linearity

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

1.0

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.5

LSB

offset error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

LSB

gain error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.3

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

load capacitance

200

load resistance



settling time

[1]

0.4

s

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